PAGE CONTENTS
Objectives
The main objective of the VOCS proposal is to design, develop, breadboard and test all the subsystems of a VDE-SAT compliant payload for small platforms such as cubesats and microsatellites. Critical breadboarding is carried out to achieve a significant reduction of DC power consumption, mass and overall volume.
Moreover, the project focuses also on the design, implementation and test of the On-Board Data Processing (OBDP) modules, related to a VDE-SAT payload.
Challenges
The major critical area of the activity is the implementation and the breadboarding, facing challenging technical issues and technology gaps.
The main technology gaps to bridge are:
- compact and light VHF duplexer and power consumption of the PA needed to close the down-link budget with 3 VDE carriers with high duty-cycle, in case of half duplex mode for cubesats
- design of RAS Filter(s) in order to be compliant with RAS normative
System Architecture
Two main architectures are envisaged: a lighter VDE-SAT payload adopting just one down-link carrier embarked on a small half-duplex Cubesat (VOCS1) on one hand, with a reduced duty-cycle to meet power budget. On the other hand, an enhanced VDE-SAT payload fully exploiting VDE-SAT with more performing antennas embarked on full-duplex small Microsatellites (VOCS2).
A third solution (VOCS-3), a full duplex solution which foresees the integration of TX and RX chain(s) on two different small satellite platforms, each of them acting as ONLY-TX or ONLY-RX, is under analysis.
The VOCS satellite architecture is based on the following key sub-components:
- Circular-polarization TX/RX VHF antenna, Yagi for VOCS2 and cross-dipole for VOCS1
- VDE-SAT Transceiver containing:
- Satellite RF front-end (SAT-FE) composed of all the analogic stages needed to manage the VHF signal between the antenna and the SDR board such as diplexer (only VOCS2), power amplifier(s), Low Noise Amplifier(s) and VHF filters
- SDR board which includes the ADCs and DACs required to perform digital to analogic and vice versa conversions as well as some RF stages such as analogic up-conversion and amplifications
- Payload On-Board Computer (pOBC), including a Programmable Logic (PL) and an Application Processing Unit (APU)
Plan
The project plan foresees a unique phase which includes the following milestones after the KO meeting (T0):
- Preliminary Design Review (T0+3M)
- Critical Design Review (T0+7M)
- Test Readiness Review (T0+16M)
- Final Review (T0+19M)
The planned total duration of the project is 19 months. The actual total project duration was 24 months.
Current Status
The project has been concluded with the Final Review meeting, held successfully on 4th July 2024.
