HTS Free Hopper

- HTS Free Hopper Beam-Hopping Demonstrator

STATUS | Ongoing
STATUS DATE | 13/04/2022
ACTIVITY CODE | 3C.026
HTS Free Hopper

Objectives

Beam Hopping is a technique which has existed on paper and in proprietary platforms for some time.  However, uptake in the wider commercial market has been constrained by the lack of an efficient standards-based approach, meaning early adopters must take on all the risks associated with a new technology.

This project aims to reduce adoption risk by making available a beam-hopping demonstrator platform which implements a wide-band FWD link transmission chain based on DVB-S2X Annex E beam-hopping features for HTS/VHTS broadband systems. The test bed will develop and integrate a DVB-S2x (Annex E Format 5, 6 and 7) GW modem prototype, BH-enabled payload breadboards based on Ferrite switching and ABFN technology, realistic channel emulation and ASIC based demodulator.

The main objective will be to validate the feasibility of a ground-space synchronisation mechanism for HTS/VHTS transparent satellite along with additional added value use cases at system, PHY layer and payload level to be identified during the project.

The test-bed platform, which is located in Airbus Toulouse, may be used in any technical or commercial scenario for interoperability testing, channel modelling and general equipment testing prior to adoption and service launch.

 

Challenges

Standards based beam-hopping technology is relatively new with the relevant DVB-S2X specification being published in March 2021.

The consortium addresses multiple hardware challenges including the building of a DVB-S2X BH capable modulator and demodulator, the implementation of a BH-capable payload (based on ferrite switch arrays and ABFN technology) and the application of realistic channel models.  The project addresses the design and implementation of a ground-space synchronisation mechanism to align asynchronous earth-based terminal equipment to the satellite respecting a given beam hopping time plans. The project involves multiple core technologies requiring coordination and integration into a coherent functional and flexible beam-hopping test-bed.

System Architecture

The test bed is automated, enabling the comprehensive and rapid evaluation of scenarios.

The automated test bench configures the equipment and sets the parameters of the beam-hopping time plan.

L-band channel emulator applies the various channel impairment whilst the ferrite switching array emulates the beam-hopping satellite.

A second modulator provides the interfering signal allowing the impact of adjacent beams to be evaluated.

A noise generator inserts AWGN. The demodulator demodulates and decodes the signal.  Various telemetry is provided such as frame rate and error rate as well as data indicating the position of the frame within the dwell time slot.

This telemetry is exploited by the ground-space synchronisation mechanism to provide feedback information to the GW modulator, therefore closing the loop and ensuring synchronisation of the terrestrial equipment with the satellite emulator.

Plan

The project is divided into two phases.

The first phase employs FPGAs to implement the demodulator.  This is because demodulator ASICs are not yet available.  The interoperability between modulator and demodulator is fully evaluated during this phase as well as a first validation of the ground-space synchronisation mechanism in a simplified test-bed set-up.

In the second phase employs an ASIC demodulator which allows testing at symbol rates up to 500Msps. During the second phase the modulator and demodulator are integrated by Airbus into the beam-hopping demonstrator platform which includes satellite channel emulation, satellite beam-hopping enabled breadboards and satellite synchronisation algorithms.

Current Status

The project kick-off date was 26/11/2021.  The project is on-going and is expected to run for 2 years (24 months).