PAGE CONTENTS
Objectives
This project aims to increase the competitivity of future satellite broadband access systems by dramatically increasing the capacity per spacecraft.
A target capacity of 50 GHz is envisaged, equivalent to 200 times the processed bandwidth of Inmarsat 4, which represents the current state of the art in transparent processed payloads. Multiple spot beam coverage will be required to achieve the necessary antenna gain and frequency reuse. In order to support the necessary flexibility in channel to beam routing, frequency mapping and channel sizing, a complex digital processor will be needed as a central element of the payload.
Such a system will require significant advances both in enabling technologies and in terms of processor algorithms and architectures. Each aspect will be investigated in detail to produce a set of candidates to be traded off in a realistic system and payload context. The objective is to obtain the optimum balance between performance, flexibility and capacity over the whole payload to maximise the competitive advantage. The selected architecture will be encapsulated in a simulation model to demonstrate the processing algorithms and system performance taking into account the effects of the overall payload.
Challenges
Among the many challenges faced by a high capacity design, some key issues are:
- Minimisation of power to fit within budget expected of future platforms,
- Antenna design to give high performance on ~200 user beams,
- Q-band technology for gateway beams,
- Filter technologies,
- Analogue and/or digital beamforming,
- Flexibility requirements for routing,
- Interconnect within the digital processor,
- Use of optical technology in the processor,
- Wideband data conversion,
- Efficient digital algorithms for demultiplexing, switching and beamforming,
- Processor packaging technology and thermal management.
Plan
The work is broken down into two phases consisting of the following tasks:
Task 1.1: Reference system scenario definition
Task 1.2: Critical review of payload and processor technologies
Task 1.3: Critical review of processor architectures
Task 1.4: High level processor architecture definition
Task 2.1: Detailed processor design
Task 2.2: Processor design validation by simulation
Current Status
The project was successfully completed and a Final Presentation made at ESTEC on 29 November 2005.
Companies
