PAGE CONTENTS
Objectives
The Small Satellites’ Software-Defined-Radio (SDR) market needs an increase in RF bandwidth and sampling frequency, in a higher number of channels and in more data processing power. This enhances even more for AI operations that requires to move to more powerful devices, using state of art FPGAs, higher component grade capability and to consider “clustering approach” for multi-channels architectures. The main objective of the SDR NeXT project is to design a software-defined reconfigurable platform using a digital board with an high-performing System on a Chip (SoC) as core.
Challenges
The SDRNeXT project targets a high-performance SDR product to penetrate the space SDR market. Herein lies a key challenge to deliver the right set of performance in the shortest possible timeframe. Time-to-market is a challenge for this complex development.
System Architecture
The SDR NeXT project, as a next generation SDR platform, is built as a modular platform, comprising four sections implemented as four electronic boards, each with embedded software serving a specific purpose.
The core is a multipurpose digital section based on the high-processing power of a SoC Zynq UltraScale+. The PCB card is designed to provide mass memory storage, high processing throughput, multiple configuration memories and high-speed communication interface.
Additional communication interface is also implemented on a second card; the communication section.
On top, a flexible and modular transceiver capacity is added with multichannel synchronous receivers and transmitters to provide high RF performances; targeting up to 9 GHz RF input and up to 500 MHz of sampling bandwidth per channel. To support this, the third section is the analogue card which has the analog front-end with Digital-to-Analogue Converters (DACs) and Analog-to-Digital Converters (ADCs) and part of the receiver (Rx) and transmitter (Tx) RF Front-End (FE) chains.
Part of the Rx and Tx channels are implemented in the RF card which provide custom specific capability and a Radio Frequency (RF) front-end.
Plan
The project is targeting a breadboard phase and prototyping phase to derisk the design and to functionally validate the design. After consolidating the electronic design with updated schematics and refined mechanics, an Engineering Model is targeted to perform a functional validation.
In the second phase, the objective is to qualify the product so that it becomes ready for the market. A Qualification Model is produced and tested during this phase. Furthermore, its industrialisation plan is targeted to define manufacturing processes, workmanship verifications and acceptance testing.
Current Status
The design, validation and qualification of the SDRNeXT product is currently ongoing.
The project has successfully passed the Requirements Review and the Preliminary Design Review.
Commercialisation and Go-to-Market Strategy is being developed.